Hardware Architecture ===================== Purpose ------- This document describes the MOTSEN Tool's hardware architecture: the major analog and power blocks, the signal chains between them, and the protection topology. It is the bridge between :doc:`../02_System/system_description` and :doc:`hardware_requirements`. The architecture is intentionally **MCU-agnostic**: the controller appears as "the MCU" with generic peripheral classes (PWM unit, ADC, GPIO, comms peripheral). Vendor- or family-specific choices belong in hardware design notes, not here. In Phase 1 the hardware is realized on an evaluation board (selection pending DEC_001); the same architecture is targeted by the custom PCB in Phase 3 (MIL_070). Architecture Overview --------------------- .. hwarch:: Overall hardware architecture :id: HWARCH_001 :status: draft :derived_from: DESC_020 The hardware is organized into seven blocks: 1. Power input and supply tree 2. Three-phase inverter (power stage) 3. Phase current sensing chain 4. DC-bus voltage sensing chain 5. Position sensor interface 6. Hardware protection 7. Host communication physical interface The MCU sits at the centre. It generates PWM into the gate drivers, samples the sensing chains via its ADC, reads position sensor signals on dedicated inputs, and exchanges frames with the host over the comms physical interface. A protection block trips the gate drivers independently of the MCU on overcurrent. .. hwarch:: Signal flow diagram :id: HWARCH_002 :status: draft :derived_from: DESC_021 .. graphviz:: digraph hw_signal_flow { rankdir=LR; node [shape=box, style="rounded,filled", fillcolor="#FADBD8"]; DCin [label="DC Input\n(12–24 V)", shape=ellipse, fillcolor="#FFF2CC"]; Supply [label="Supply Tree\n(logic / analog / gate-drv)"]; GDrv [label="Gate Drivers"]; Inv [label="3× Half-Bridge\n(Power FETs)"]; IShunt [label="Phase Current\nSense"]; VBus [label="DC-Bus\nVoltage Sense"]; PosIF [label="Position\nSensor IF"]; OC [label="HW Overcurrent\nLatch"]; MCU [label="MCU\n(generic)", fillcolor="#D6EAF8"]; Link [label="Host Link\nTransceiver"]; Motor [label="Motor\n(phases + sensors)", shape=ellipse, fillcolor="#FFF2CC"]; Host [label="Host PC", shape=ellipse, fillcolor="#FFF2CC"]; DCin -> Supply; DCin -> Inv [label="DC bus"]; Supply -> MCU; Supply -> GDrv; Supply -> PosIF; MCU -> GDrv [label="PWM"]; GDrv -> Inv [label="gate"]; Inv -> Motor [label="3-phase"]; Motor -> PosIF; Inv -> IShunt; Inv -> VBus; IShunt -> MCU [label="ADC"]; VBus -> MCU [label="ADC"]; PosIF -> MCU [label="digital / ADC"]; IShunt -> OC; OC -> GDrv [label="disable"]; MCU -> OC [label="arm / reset"]; MCU -> Link; Link -> Host; Host -> Link; Link -> MCU; } Power Input and Supply Tree --------------------------- .. hwarch:: DC input and bus :id: HWARCH_010 :status: draft :derived_from: DESC_030 :linked_to: DEC_001 The board accepts a single DC input that becomes the inverter DC bus. Working range is 12–24 V for the MVP envelope. A reverse-polarity device and bulk bus capacitance sit between the input and the inverter. Final ratings (voltage tolerance, peak/continuous current, capacitance) are pending DEC_001. .. hwarch:: Logic and analog supply rails :id: HWARCH_011 :status: draft :derived_from: DESC_030 The supply tree derives the rails needed by the controller and analog front-end from the DC input: * A logic rail for the MCU and digital circuitry. * An analog rail for ADC references and signal-conditioning amplifiers. * Gate-driver supplies appropriate to the chosen driver topology. Logic and analog rails are separated in their routing and decoupling. The ADC reference is generated locally and is not the same node as the logic supply. .. hwarch:: Sequencing and brown-out :id: HWARCH_012 :status: draft :derived_from: DESC_034 The supply tree ensures the MCU is in reset until its logic rail is in tolerance, so that gate-drive inputs are never driven during power-up. Brown-out behavior of the MCU rail forces the same condition on the way down. Three-Phase Inverter -------------------- .. hwarch:: Half-bridge topology :id: HWARCH_020 :status: draft :derived_from: DESC_030 The power stage consists of three identical half-bridges driving the motor phases. Each half-bridge is driven by a dedicated gate-driver channel that accepts a single PWM input and produces complementary high-side / low-side gate drive with hardware-enforced dead-time. .. hwarch:: Gate drive :id: HWARCH_021 :status: draft :derived_from: DESC_030 The gate drivers provide: * Level translation from MCU PWM levels to gate-drive levels. * Hardware dead-time, configurable in hardware or fixed depending on the selected driver. * A common shutdown input wired to the protection block (see :need:`HWARCH_060`). .. hwarch:: Output filtering and snubbing :id: HWARCH_022 :status: draft :derived_from: DESC_030 Each switch node and the DC bus include the snubbing and decoupling required for clean switching transitions at the target switching frequency. Output filters between the half-bridges and the motor are not included; the motor inductance is the only filter element on the AC side. Phase Current Sensing --------------------- .. hwarch:: Low-side shunt topology :id: HWARCH_030 :status: draft :derived_from: DESC_031 Phase current is sensed by a shunt resistor in the low-side return path of each half-bridge. A differential amplifier conditions the shunt voltage into the ADC input range with a bias chosen to allow bipolar current measurement. .. hwarch:: PWM-synchronous sampling :id: HWARCH_031 :status: draft :derived_from: DESC_031 The ADC sampling instants are aligned with the PWM cycle so that phase currents are sampled while the low-side switches are conducting (typically at the centre of the PWM period for center-aligned modulation). .. hwarch:: Sense bandwidth and anti-aliasing :id: HWARCH_032 :status: draft :derived_from: DESC_031 Each current sense channel includes an analog low-pass filter chosen so that the noise floor is bounded above the ADC quantization but below the target measurement precision, and so that switching ripple is attenuated below the ADC's aliasing band at the sampling rate. DC-Bus Voltage Sensing ---------------------- .. hwarch:: DC-bus divider :id: HWARCH_040 :status: draft :derived_from: DESC_031 The DC-bus voltage is sensed by a resistive divider scaled to map the full bus range into the ADC input range, followed by an anti-alias filter sized for the bus-sense bandwidth (lower than the current-sense bandwidth). .. hwarch:: Bus sense as protection input :id: HWARCH_041 :status: draft :derived_from: DESC_034 The bus-sense signal is read by the MCU ADC and is also available as an input to the protection block for over-voltage detection independent of the firmware. Position Sensor Interface ------------------------- .. hwarch:: Hall sensor interface :id: HWARCH_050 :status: draft :derived_from: DESC_032 Three Hall sensor inputs are provided. Each input is conditioned for open-collector and push-pull sensor outputs, with input pull-ups, over-voltage protection, and an RC debounce filter sized for the maximum expected commutation rate. .. hwarch:: Incremental encoder interface :id: HWARCH_051 :status: placeholder :derived_from: DESC_032 :linked_to: MIL_042 A/B/Z encoder inputs supporting both single-ended and differential signals. Scheduled for Phase 2 (MIL_042). .. hwarch:: Resolver interface :id: HWARCH_052 :status: placeholder :derived_from: DESC_032 :linked_to: MIL_077 Resolver excitation and sin/cos demodulation. Scheduled for Phase 3 (MIL_077). .. hwarch:: Sensor supply :id: HWARCH_053 :status: draft :derived_from: DESC_032 Position sensor supply is provided from the analog-clean rail with current limiting and short-circuit protection on the connector pin so that a shorted or miswired sensor cable cannot collapse the analog rail. MCU Interface ------------- .. hwarch:: MCU peripheral classes used :id: HWARCH_060 :status: draft :derived_from: DESC_033 The architecture requires the following peripheral classes from the MCU, regardless of vendor: * A 3-phase center-aligned PWM unit with complementary outputs and ADC trigger generation. * An ADC capable of sampling at least the three phase-current and one DC-bus channels within a single PWM period. * GPIO inputs suitable for Hall sensors with optional interrupt capability. * One asynchronous serial comms peripheral for the host link (UART or equivalent). * A general-purpose timer for the system tick. Specific MCU families and the binding of these peripheral classes are handled in firmware via the HAL (see :doc:`../04_Software/software_architecture`). .. hwarch:: MCU pin grouping :id: HWARCH_061 :status: draft :derived_from: DESC_033 MCU pins are grouped by function: PWM out, current-sense ADC in, bus-sense ADC in, position-sensor in, protection in/out, host-link, debug. Routing respects these groups so that signals from the same group share return paths and references. .. hwarch:: Debug and program interface :id: HWARCH_062 :status: draft :derived_from: DESC_033 A standard debug connector exposes the MCU's debug and reset signals. The connector type and pinout are chosen to be compatible with the project's flashing path (Ozone / J-Link), but no MCU-specific debug protocol is assumed at the architecture level. Hardware Protection ------------------- .. hwarch:: Overcurrent latch :id: HWARCH_070 :status: draft :derived_from: DESC_034 A hardware comparator monitors the summed low-side current (or per-phase current, depending on topology) against a hardware-set threshold. A trip sets a latch whose output forces the gate-driver shutdown input active, independently of the MCU. .. hwarch:: Latch reset path :id: HWARCH_071 :status: draft :derived_from: DESC_034 The latch is reset only by an explicit MCU action (e.g. a dedicated GPIO pulse). Power-on state is "tripped" so that the inverter cannot switch until the firmware has armed itself. .. hwarch:: Bus over-voltage shutdown :id: HWARCH_072 :status: draft :derived_from: DESC_034 A second comparator on the DC-bus sense signal asserts the same shutdown path on bus over-voltage, providing protection against regenerative braking transients independent of the firmware. .. hwarch:: Watchdog supervision :id: HWARCH_073 :status: draft :derived_from: DESC_034 An external watchdog (or the MCU's internal watchdog wired to assert the shutdown path) ensures that loss of firmware activity also disables the inverter. Host Communication Physical Interface ------------------------------------- .. hwarch:: Host link transceiver :id: HWARCH_080 :status: placeholder :derived_from: DESC_035 :linked_to: DEC_003 A single host-link transceiver and connector are provided. The physical choice (USB device, UART-over-USB bridge, isolated UART) is pending DEC_003. .. hwarch:: Host link isolation :id: HWARCH_081 :status: draft :derived_from: DESC_035 The host-link physical interface is electrically isolated from the power stage's signal ground, or a single-point ground connection between the host link and the power-stage ground is documented. This protects the host PC from inverter switching transients. .. hwarch:: CAN physical layer :id: HWARCH_082 :status: placeholder :derived_from: DESC_035 :linked_to: MIL_043 A CAN transceiver and connector are provided. Scheduled for Phase 2 (MIL_043). Connectors and External Interfaces ---------------------------------- .. hwarch:: External connectors :id: HWARCH_090 :status: draft :derived_from: DESC_010 External connectors at the system boundary are: * DC input. * Three motor-phase outputs. * Position sensor connector(s). * Host link. * Optional CAN. * Debug. Each connector is keyed or otherwise mechanically distinct from the others to prevent miswiring at the bench. Open Items ---------- .. hwarch:: Final power-stage ratings — pending :id: HWARCH_900 :status: placeholder :derived_from: DESC_060 :linked_to: DEC_001 Voltage, current, switching frequency, gate-driver topology, and current- sense scaling are pending DEC_001 (eval board selection in Phase 1). .. hwarch:: Host link physical layer — pending :id: HWARCH_901 :status: placeholder :derived_from: DESC_061 :linked_to: DEC_003 Physical layer (UART vs USB-CDC vs isolated UART) is pending DEC_003. .. hwarch:: Custom PCB form factor — pending :id: HWARCH_902 :status: placeholder :derived_from: DESC_050 :linked_to: MIL_070 Mechanical form factor, connector arrangement, and mounting are pending the Phase 3 custom PCB (MIL_070). Traceability ------------ Each ``hwarch`` node above declares ``derived_from`` exactly one ``DESC_*`` node in :doc:`../02_System/system_description`. The forward direction is populated by ``hwreq`` nodes in :doc:`hardware_requirements`, which declare ``derived_from`` either a ``SYS_*`` requirement or an ``HWARCH_*`` block here.