Hardware Requirements ===================== Purpose ------- This document lists the hardware-level requirements for the MOTSEN Tool. Each requirement is a small testable "shall" statement derived from a single ``HWARCH_*`` block in :doc:`hardware_architecture` or, where the hardware is the primary realization of a system behavior, directly from a ``SYS_*`` node in :doc:`../02_System/system_requirements`. Conventions: * One requirement, one verb, one observable property. * ``derived_from`` points to exactly one ``HWARCH_*`` or ``SYS_*``. * Numeric values that depend on the eval-board selection (DEC_001) or other open decisions are written as ``status: placeholder`` until those decisions close. * All requirements are MCU-agnostic; the MCU is referenced only as "the MCU". Power Input ----------- .. hwreq:: DC input voltage range :id: HWREQ_001 :status: draft :derived_from: HWARCH_010 The board shall operate from a DC input in the range 12 V to 24 V. .. hwreq:: Reverse polarity protection :id: HWREQ_002 :status: draft :derived_from: HWARCH_010 The DC input shall survive reverse polarity application without damage to the board. .. hwreq:: Continuous input current :id: HWREQ_003 :status: placeholder :derived_from: HWARCH_010 :linked_to: DEC_001 Continuous and peak DC input current ratings are pending DEC_001. Supply Tree ----------- .. hwreq:: Separated analog and logic rails :id: HWREQ_010 :status: draft :derived_from: HWARCH_011 Analog and digital supply rails shall be separated from each other in their routing and decoupling, sharing the input only at a single defined point. .. hwreq:: Local ADC reference :id: HWREQ_011 :status: draft :derived_from: HWARCH_011 The ADC reference shall be generated from a dedicated low-noise source and shall not be electrically the same node as the digital supply. .. hwreq:: Power sequencing :id: HWREQ_012 :status: draft :derived_from: HWARCH_012 The MCU shall remain in reset until its logic rail is within the manufacturer-specified tolerance. Three-Phase Inverter -------------------- .. hwreq:: Three independent half-bridges :id: HWREQ_020 :status: draft :derived_from: HWARCH_020 The power stage shall provide three independent half-bridges driving the three motor phases. .. hwreq:: Complementary gate drive with dead-time :id: HWREQ_021 :status: draft :derived_from: HWARCH_021 Each half-bridge shall be driven by complementary high-side / low-side signals with a non-zero dead-time enforced in hardware. .. hwreq:: Gate-driver shutdown input :id: HWREQ_022 :status: draft :derived_from: HWARCH_021 Each gate driver shall expose a shutdown input that forces both high-side and low-side outputs to the off state regardless of the PWM input. .. hwreq:: Output high-impedance on disable :id: HWREQ_023 :status: draft :derived_from: HWARCH_020 When the gate-driver shutdown input is asserted, all three phase outputs shall be high-impedance within one PWM period. .. hwreq:: Output voltage and current ratings :id: HWREQ_024 :status: placeholder :derived_from: HWARCH_020 :linked_to: DEC_001 Output continuous current, peak current, and switching frequency ratings are pending DEC_001. Phase Current Sensing --------------------- .. hwreq:: Per-phase current sense :id: HWREQ_030 :status: draft :derived_from: HWARCH_030 Each motor phase shall have an independent low-side current-sense channel. .. hwreq:: Bipolar current range :id: HWREQ_031 :status: draft :derived_from: HWARCH_030 Each current-sense channel shall measure current bipolarly (positive and negative) within the full operating range of the inverter. .. hwreq:: Current-sense bandwidth :id: HWREQ_032 :status: draft :derived_from: HWARCH_032 Each current-sense channel shall have a -3 dB bandwidth sufficient to resolve the current waveform at the maximum target electrical frequency, while attenuating PWM switching ripple below the ADC's aliasing band. .. hwreq:: Current-sense accuracy :id: HWREQ_033 :status: draft :derived_from: SYS_044 Each current-sense channel shall achieve, after calibration, an absolute accuracy sufficient for the Rs measurement tolerance defined in :need:`SYS_101`. The numeric tolerance closes when the eval board is selected (DEC_001). .. hwreq:: PWM-synchronous ADC trigger :id: HWREQ_034 :status: draft :derived_from: HWARCH_031 The hardware shall provide a means for the MCU's PWM unit to trigger the ADC sampling of all current-sense channels at the same instant within the PWM cycle. DC-Bus Voltage Sensing ---------------------- .. hwreq:: Bus voltage measurement :id: HWREQ_040 :status: draft :derived_from: HWARCH_040 The hardware shall measure the DC-bus voltage with the ADC. .. hwreq:: Bus voltage range :id: HWREQ_041 :status: draft :derived_from: HWARCH_040 The bus-sense divider shall map the full operating range of the bus into the ADC input range with at least 10% margin on the upper end. .. hwreq:: Bus voltage comparator :id: HWREQ_042 :status: draft :derived_from: HWARCH_041 A hardware comparator shall be available on the bus-sense signal and shall feed the protection block on over-voltage. Position Sensor Interface ------------------------- .. hwreq:: Three Hall sensor inputs :id: HWREQ_050 :status: draft :derived_from: HWARCH_050 The board shall provide three Hall sensor inputs. .. hwreq:: Hall input compatibility :id: HWREQ_051 :status: draft :derived_from: HWARCH_050 Each Hall input shall accept open-collector and push-pull sensor outputs in the 3.3–5 V range without modification. .. hwreq:: Hall input over-voltage tolerance :id: HWREQ_052 :status: draft :derived_from: HWARCH_050 Each Hall input shall survive momentary application of the sensor supply voltage to ground without damage. .. hwreq:: Sensor supply current limit :id: HWREQ_053 :status: draft :derived_from: HWARCH_053 The sensor supply rail at the connector shall be current-limited such that a short to ground does not collapse any other analog rail on the board. .. hwreq:: Encoder inputs :id: HWREQ_054 :status: placeholder :derived_from: HWARCH_051 :linked_to: MIL_042 The board shall provide A/B/Z encoder inputs supporting single-ended and differential signals. Scheduled for Phase 2 (MIL_042). .. hwreq:: Resolver excitation and sense :id: HWREQ_055 :status: placeholder :derived_from: HWARCH_052 :linked_to: MIL_077 The board shall provide resolver excitation output and sin/cos sense inputs. Scheduled for Phase 3 (MIL_077). MCU Interface ------------- .. hwreq:: PWM unit availability :id: HWREQ_060 :status: draft :derived_from: HWARCH_060 The MCU shall expose a 3-phase center-aligned PWM unit with complementary outputs and an ADC trigger. .. hwreq:: ADC channel count and rate :id: HWREQ_061 :status: draft :derived_from: HWARCH_060 The MCU's ADC subsystem shall sample at least three phase-current channels plus the DC-bus channel within a single PWM period. .. hwreq:: Hall input mapping :id: HWREQ_062 :status: draft :derived_from: HWARCH_060 The MCU shall route the three Hall sensor inputs to GPIO pins that support edge interrupts. .. hwreq:: Debug connector :id: HWREQ_063 :status: draft :derived_from: HWARCH_062 A debug connector shall be provided exposing the MCU's debug and reset signals, with a pinout compatible with the project's flashing tool path (Ozone / J-Link). Protection ---------- .. hwreq:: Hardware overcurrent latch :id: HWREQ_070 :status: draft :derived_from: HWARCH_070 The board shall include a hardware overcurrent latch whose output forces the gate-driver shutdown input active independently of the MCU. .. hwreq:: Latch reset by MCU only :id: HWREQ_071 :status: draft :derived_from: HWARCH_071 The overcurrent latch shall be reset only by an explicit MCU action. The latch shall be in the tripped state at power-on. .. hwreq:: Bus over-voltage shutdown :id: HWREQ_072 :status: draft :derived_from: HWARCH_072 The board shall trip the gate-driver shutdown path when the DC-bus voltage exceeds a hardware-set threshold, independently of the MCU. .. hwreq:: Watchdog supervision :id: HWREQ_073 :status: draft :derived_from: HWARCH_073 The board shall assert the gate-driver shutdown path on loss of MCU activity, using either an external watchdog or a watchdog signal from the MCU's internal watchdog. .. hwreq:: Overcurrent trip threshold :id: HWREQ_074 :status: placeholder :derived_from: HWARCH_070 :linked_to: DEC_001 The numeric overcurrent trip threshold is pending DEC_001. Host Communication Physical Interface ------------------------------------- .. hwreq:: Host link transceiver :id: HWREQ_080 :status: placeholder :derived_from: HWARCH_080 :linked_to: DEC_003 The board shall include a transceiver and connector for the host link. The choice of physical layer is pending DEC_003. .. hwreq:: Host link isolation :id: HWREQ_081 :status: draft :derived_from: HWARCH_081 The host link shall either be galvanically isolated from the power-stage ground, or its single-point ground connection shall be documented. .. hwreq:: CAN transceiver :id: HWREQ_082 :status: placeholder :derived_from: HWARCH_082 :linked_to: MIL_043 The board shall include a CAN transceiver and connector. Scheduled for Phase 2 (MIL_043). Connectors ---------- .. hwreq:: Distinct mechanical keying :id: HWREQ_090 :status: draft :derived_from: HWARCH_090 Each external connector shall be mechanically or visually distinct from every other external connector such that a user cannot insert a cable into the wrong connector. .. hwreq:: Connector list :id: HWREQ_091 :status: draft :derived_from: HWARCH_090 The board shall expose at minimum: a DC-input connector, a three-phase motor-output connector, a position-sensor connector, a host-link connector, and a debug connector. Environmental and Mechanical ---------------------------- .. hwreq:: Bench operating temperature :id: HWREQ_100 :status: draft :derived_from: HWARCH_001 The board shall operate at indoor bench ambient temperatures of 10 °C to 35 °C without forced cooling, at the rated continuous output. .. hwreq:: Custom PCB form factor :id: HWREQ_101 :status: placeholder :derived_from: HWARCH_902 :linked_to: MIL_070 The custom PCB shall be specified for mechanical dimensions, mounting, and connector positions. Scheduled for Phase 3 (MIL_070). Open Items ---------- .. hwreq:: Final power-stage ratings — pending :id: HWREQ_900 :status: placeholder :derived_from: HWARCH_900 :linked_to: DEC_001 Final ratings for the power stage close with DEC_001 (eval board selection in Phase 1; custom PCB in Phase 3). .. hwreq:: Host link physical layer — pending :id: HWREQ_901 :status: placeholder :derived_from: HWARCH_901 :linked_to: DEC_003 Final host link physical layer closes with DEC_003. Traceability ------------ Forward links from ``hwreq`` to hardware test cases (``TEST_*`` in :doc:`hardware_test_plan`) will be added as the hardware test plan is populated.