Hardware Architecture¶
Purpose¶
This document describes the MOTSEN Tool’s hardware architecture: the major analog and power blocks, the signal chains between them, and the protection topology. It is the bridge between System Description and Hardware Requirements.
The architecture is intentionally MCU-agnostic: the controller appears as “the MCU” with generic peripheral classes (PWM unit, ADC, GPIO, comms peripheral). Vendor- or family-specific choices belong in hardware design notes, not here.
In Phase 1 the hardware is realized on an evaluation board (selection pending DEC_001); the same architecture is targeted by the custom PCB in Phase 3 (MIL_070).
Architecture Overview¶
The hardware is organized into seven blocks:
The MCU sits at the centre. It generates PWM into the gate drivers, samples the sensing chains via its ADC, reads position sensor signals on dedicated inputs, and exchanges frames with the host over the comms physical interface. A protection block trips the gate drivers independently of the MCU on overcurrent. |
| digraph hw_signal_flow { rankdir=LR; node [shape=box, style="rounded,filled", fillcolor="#FADBD8"]; DCin [label="DC Input\n(12–24 V)", shape=ellipse, fillcolor="#FFF2CC"]; Supply [label="Supply Tree\n(logic / analog / gate-drv)"]; GDrv [label="Gate Drivers"]; Inv [label="3× Half-Bridge\n(Power FETs)"]; IShunt [label="Phase Current\nSense"]; VBus [label="DC-Bus\nVoltage Sense"]; PosIF [label="Position\nSensor IF"]; OC [label="HW Overcurrent\nLatch"]; MCU [label="MCU\n(generic)", fillcolor="#D6EAF8"]; Link [label="Host Link\nTransceiver"]; Motor [label="Motor\n(phases + sensors)", shape=ellipse, fillcolor="#FFF2CC"]; Host [label="Host PC", shape=ellipse, fillcolor="#FFF2CC"]; DCin -> Supply; DCin -> Inv [label="DC bus"]; Supply -> MCU; Supply -> GDrv; Supply -> PosIF; MCU -> GDrv [label="PWM"]; GDrv -> Inv [label="gate"]; Inv -> Motor [label="3-phase"]; Motor -> PosIF; Inv -> IShunt; Inv -> VBus; IShunt -> MCU [label="ADC"]; VBus -> MCU [label="ADC"]; PosIF -> MCU [label="digital / ADC"]; IShunt -> OC; OC -> GDrv [label="disable"]; MCU -> OC [label="arm / reset"]; MCU -> Link; Link -> Host; Host -> Link; Link -> MCU; } |
Power Input and Supply Tree¶
The board accepts a single DC input that becomes the inverter DC bus. Working range is 12–24 V for the MVP envelope. A reverse-polarity device and bulk bus capacitance sit between the input and the inverter. Final ratings (voltage tolerance, peak/continuous current, capacitance) are pending DEC_001. |
The supply tree derives the rails needed by the controller and analog front-end from the DC input:
Logic and analog rails are separated in their routing and decoupling. The ADC reference is generated locally and is not the same node as the logic supply. |
The supply tree ensures the MCU is in reset until its logic rail is in tolerance, so that gate-drive inputs are never driven during power-up. Brown-out behavior of the MCU rail forces the same condition on the way down. |
Three-Phase Inverter¶
The power stage consists of three identical half-bridges driving the motor phases. Each half-bridge is driven by a dedicated gate-driver channel that accepts a single PWM input and produces complementary high-side / low-side gate drive with hardware-enforced dead-time. |
The gate drivers provide:
|
Each switch node and the DC bus include the snubbing and decoupling required for clean switching transitions at the target switching frequency. Output filters between the half-bridges and the motor are not included; the motor inductance is the only filter element on the AC side. |
Phase Current Sensing¶
Phase current is sensed by a shunt resistor in the low-side return path of each half-bridge. A differential amplifier conditions the shunt voltage into the ADC input range with a bias chosen to allow bipolar current measurement. |
The ADC sampling instants are aligned with the PWM cycle so that phase currents are sampled while the low-side switches are conducting (typically at the centre of the PWM period for center-aligned modulation). |
Each current sense channel includes an analog low-pass filter chosen so that the noise floor is bounded above the ADC quantization but below the target measurement precision, and so that switching ripple is attenuated below the ADC’s aliasing band at the sampling rate. |
DC-Bus Voltage Sensing¶
The DC-bus voltage is sensed by a resistive divider scaled to map the full bus range into the ADC input range, followed by an anti-alias filter sized for the bus-sense bandwidth (lower than the current-sense bandwidth). |
The bus-sense signal is read by the MCU ADC and is also available as an input to the protection block for over-voltage detection independent of the firmware. |
Position Sensor Interface¶
Three Hall sensor inputs are provided. Each input is conditioned for open-collector and push-pull sensor outputs, with input pull-ups, over-voltage protection, and an RC debounce filter sized for the maximum expected commutation rate. |
A/B/Z encoder inputs supporting both single-ended and differential signals. Scheduled for Phase 2 (MIL_042). |
Resolver excitation and sin/cos demodulation. Scheduled for Phase 3 (MIL_077). |
Position sensor supply is provided from the analog-clean rail with current limiting and short-circuit protection on the connector pin so that a shorted or miswired sensor cable cannot collapse the analog rail. |
MCU Interface¶
The architecture requires the following peripheral classes from the MCU, regardless of vendor:
Specific MCU families and the binding of these peripheral classes are handled in firmware via the HAL (see Software Architecture). |
MCU pins are grouped by function: PWM out, current-sense ADC in, bus-sense ADC in, position-sensor in, protection in/out, host-link, debug. Routing respects these groups so that signals from the same group share return paths and references. |
A standard debug connector exposes the MCU’s debug and reset signals. The connector type and pinout are chosen to be compatible with the project’s flashing path (Ozone / J-Link), but no MCU-specific debug protocol is assumed at the architecture level. |
Hardware Protection¶
A hardware comparator monitors the summed low-side current (or per-phase current, depending on topology) against a hardware-set threshold. A trip sets a latch whose output forces the gate-driver shutdown input active, independently of the MCU. |
The latch is reset only by an explicit MCU action (e.g. a dedicated GPIO pulse). Power-on state is “tripped” so that the inverter cannot switch until the firmware has armed itself. |
A second comparator on the DC-bus sense signal asserts the same shutdown path on bus over-voltage, providing protection against regenerative braking transients independent of the firmware. |
An external watchdog (or the MCU’s internal watchdog wired to assert the shutdown path) ensures that loss of firmware activity also disables the inverter. |
Host Communication Physical Interface¶
A single host-link transceiver and connector are provided. The physical choice (USB device, UART-over-USB bridge, isolated UART) is pending DEC_003. |
The host-link physical interface is electrically isolated from the power stage’s signal ground, or a single-point ground connection between the host link and the power-stage ground is documented. This protects the host PC from inverter switching transients. |
A CAN transceiver and connector are provided. Scheduled for Phase 2 (MIL_043). |
Connectors and External Interfaces¶
External connectors at the system boundary are:
Each connector is keyed or otherwise mechanically distinct from the others to prevent miswiring at the bench. |
Open Items¶
Voltage, current, switching frequency, gate-driver topology, and current- sense scaling are pending DEC_001 (eval board selection in Phase 1). |
Physical layer (UART vs USB-CDC vs isolated UART) is pending DEC_003. |
Mechanical form factor, connector arrangement, and mounting are pending the Phase 3 custom PCB (MIL_070). |
Traceability¶
Each hwarch node above declares derived_from exactly one DESC_*
node in System Description. The forward direction is
populated by hwreq nodes in Hardware Requirements, which declare
derived_from either a SYS_* requirement or an HWARCH_* block here.