Hardware Requirements¶
Purpose¶
This document lists the hardware-level requirements for the MOTSEN Tool. Each
requirement is a small testable “shall” statement derived from a single
HWARCH_* block in Hardware Architecture or, where the hardware is
the primary realization of a system behavior, directly from a SYS_* node
in System Requirements.
Conventions:
One requirement, one verb, one observable property.
derived_frompoints to exactly oneHWARCH_*orSYS_*.Numeric values that depend on the eval-board selection (DEC_001) or other open decisions are written as
status: placeholderuntil those decisions close.All requirements are MCU-agnostic; the MCU is referenced only as “the MCU”.
Power Input¶
The board shall operate from a DC input in the range 12 V to 24 V. |
The DC input shall survive reverse polarity application without damage to the board. |
Continuous and peak DC input current ratings are pending DEC_001. |
Supply Tree¶
Analog and digital supply rails shall be separated from each other in their routing and decoupling, sharing the input only at a single defined point. |
The ADC reference shall be generated from a dedicated low-noise source and shall not be electrically the same node as the digital supply. |
The MCU shall remain in reset until its logic rail is within the manufacturer-specified tolerance. |
Three-Phase Inverter¶
The power stage shall provide three independent half-bridges driving the three motor phases. |
Each half-bridge shall be driven by complementary high-side / low-side signals with a non-zero dead-time enforced in hardware. |
Each gate driver shall expose a shutdown input that forces both high-side and low-side outputs to the off state regardless of the PWM input. |
When the gate-driver shutdown input is asserted, all three phase outputs shall be high-impedance within one PWM period. |
Output continuous current, peak current, and switching frequency ratings are pending DEC_001. |
Phase Current Sensing¶
Each motor phase shall have an independent low-side current-sense channel. |
Each current-sense channel shall measure current bipolarly (positive and negative) within the full operating range of the inverter. |
Each current-sense channel shall have a -3 dB bandwidth sufficient to resolve the current waveform at the maximum target electrical frequency, while attenuating PWM switching ripple below the ADC’s aliasing band. |
Each current-sense channel shall achieve, after calibration, an absolute accuracy sufficient for the Rs measurement tolerance defined in Rs accuracy against referen... (SYS_101). The numeric tolerance closes when the eval board is selected (DEC_001). |
The hardware shall provide a means for the MCU’s PWM unit to trigger the ADC sampling of all current-sense channels at the same instant within the PWM cycle. |
DC-Bus Voltage Sensing¶
The hardware shall measure the DC-bus voltage with the ADC. |
The bus-sense divider shall map the full operating range of the bus into the ADC input range with at least 10% margin on the upper end. |
A hardware comparator shall be available on the bus-sense signal and shall feed the protection block on over-voltage. |
Position Sensor Interface¶
The board shall provide three Hall sensor inputs. |
Each Hall input shall accept open-collector and push-pull sensor outputs in the 3.3–5 V range without modification. |
Each Hall input shall survive momentary application of the sensor supply voltage to ground without damage. |
The sensor supply rail at the connector shall be current-limited such that a short to ground does not collapse any other analog rail on the board. |
The board shall provide A/B/Z encoder inputs supporting single-ended and differential signals. Scheduled for Phase 2 (MIL_042). |
The board shall provide resolver excitation output and sin/cos sense inputs. Scheduled for Phase 3 (MIL_077). |
MCU Interface¶
The MCU shall expose a 3-phase center-aligned PWM unit with complementary outputs and an ADC trigger. |
The MCU’s ADC subsystem shall sample at least three phase-current channels plus the DC-bus channel within a single PWM period. |
The MCU shall route the three Hall sensor inputs to GPIO pins that support edge interrupts. |
A debug connector shall be provided exposing the MCU’s debug and reset signals, with a pinout compatible with the project’s flashing tool path (Ozone / J-Link). |
Protection¶
The board shall include a hardware overcurrent latch whose output forces the gate-driver shutdown input active independently of the MCU. |
The overcurrent latch shall be reset only by an explicit MCU action. The latch shall be in the tripped state at power-on. |
The board shall trip the gate-driver shutdown path when the DC-bus voltage exceeds a hardware-set threshold, independently of the MCU. |
The board shall assert the gate-driver shutdown path on loss of MCU activity, using either an external watchdog or a watchdog signal from the MCU’s internal watchdog. |
The numeric overcurrent trip threshold is pending DEC_001. |
Host Communication Physical Interface¶
The board shall include a transceiver and connector for the host link. The choice of physical layer is pending DEC_003. |
The host link shall either be galvanically isolated from the power-stage ground, or its single-point ground connection shall be documented. |
The board shall include a CAN transceiver and connector. Scheduled for Phase 2 (MIL_043). |
Connectors¶
Each external connector shall be mechanically or visually distinct from every other external connector such that a user cannot insert a cable into the wrong connector. |
The board shall expose at minimum: a DC-input connector, a three-phase motor-output connector, a position-sensor connector, a host-link connector, and a debug connector. |
Environmental and Mechanical¶
The board shall operate at indoor bench ambient temperatures of 10 °C to 35 °C without forced cooling, at the rated continuous output. |
The custom PCB shall be specified for mechanical dimensions, mounting, and connector positions. Scheduled for Phase 3 (MIL_070). |
Open Items¶
Final ratings for the power stage close with DEC_001 (eval board selection in Phase 1; custom PCB in Phase 3). |
Final host link physical layer closes with DEC_003. |
Traceability¶
Forward links from hwreq to hardware test cases (TEST_* in
<no title>) will be added as the hardware test plan is
populated.